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Garnet: A Detailed on-Chip Network Model inside a Full-System Simulator

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dc.contributor Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.contributor Peh, Li-Shiuan
dc.creator Agarwal, Niket
dc.creator Krishna, Tushar
dc.creator Peh, Li-Shiuan
dc.creator Jha, Niraj K.
dc.date 2012-10-01T15:55:56Z
dc.date 2012-10-01T15:55:56Z
dc.date 2009-05
dc.date 2009-04
dc.date.accessioned 2023-03-01T18:08:15Z
dc.date.available 2023-03-01T18:08:15Z
dc.identifier 978-1-4244-4184-6
dc.identifier http://hdl.handle.net/1721.1/73506
dc.identifier Agarwal, Niket et al. “GARNET: A Detailed On-chip Network Model Inside a Full-system Simulator.” IEEE International Symposium on Performance Analysis of Systems and Software, 2009. ISPASS 2009. 33–42. © Copyright 2009 IEEE
dc.identifier https://orcid.org/0000-0001-9010-6519
dc.identifier.uri http://localhost:8080/xmlui/handle/CUHPOERS/278889
dc.description Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. The interconnect power was also insignificant compared to the transistor power. With uniprocessor designs providing diminishing returns and the advent of chip multiprocessors (CMPs) in mainstream systems, the on-chip network that connects different processing cores has become a critical part of the design. Transistor miniaturization has led to high global wire delay, and interconnect power comparable to transistor power. CMP design proposals can no longer ignore the interaction between the memory hierarchy and the interconnection network that connects various elements. This necessitates a detailed and accurate interconnection network model within a full-system evaluation framework. Ignoring the interconnect details might lead to inaccurate results when simulating a CMP architecture. It also becomes important to analyze the impact of interconnection network optimization techniques on full system behavior. In this light, we developed a detailed cycle-accurate interconnection network model (GARNET), inside the GEMS full-system simulation framework. GARNET models a classic five-stage pipelined router with virtual channel (VC) flow control. Microarchitectural details, such as flit-level input buffers, routing logic, allocators and the crossbar switch, are modeled. GARNET, along with GEMS, provides a detailed and accurate memory system timing model. To demonstrate the importance and potential impact of GARNET, we evaluate a shared and private L2 CMP with a realistic state-of-the-art interconnection network against the original GEMS simple network. The objective of the evaluation was to figure out which configuration is better for a particular workload. We show that not modeling the interconnect in detail might lead to an incorrect outcome. We also evaluate Express Virtual Channels (EVCs), an on-ch- ip network flow control proposal, in a full-system fashion. We show that in improving on-chip network latency-throughput, EVCs do lead to better overall system runtime, however, the impact varies widely across applications.
dc.description National Science Foundation (U.S.) (Grant CNS- 0613074)
dc.description Microelectronics Advanced Research Corporation (MARCO) Gigascale Systems Research Center and SRC (Contract 2008-HJ-1793)
dc.format application/pdf
dc.language en_US
dc.publisher Institute of Electrical and Electronics Engineers (IEEE)
dc.relation http://dx.doi.org/10.1109/ISPASS.2009.4919636
dc.relation Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009. ISPASS 2009
dc.rights Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
dc.source IEEE
dc.title Garnet: A Detailed on-Chip Network Model inside a Full-System Simulator
dc.type Article
dc.type http://purl.org/eprint/type/ConferencePaper


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